#ifndef F28P65X_CLA_H
#define F28P65X_CLA_H

#ifdef __cplusplus
extern "C" {
#endif

//---------------------------------------------------------------------------
// CLA Individual Register Bit Definitions:

struct MCTL_BITS
{                          // bits description
    Uint32 HARDRESET : 1;  // 0 Hard Reset
    Uint32 SOFTRESET : 1;  // 1 Soft Reset
    Uint32 IACKE     : 1;  // 2 IACK enable
    Uint32 rsvd1     : 13; // 15:3 Reserved
    Uint32 rsvd2     : 16; // 31:16 Reserved
};

union MCTL_REG
{
    Uint32 all;
    struct MCTL_BITS bit;
};

struct MIFR_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Flag
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Flag
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Flag
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Flag
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Flag
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Flag
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Flag
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Flag
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MIFR_REG
{
    Uint32 all;
    struct MIFR_BITS bit;
};

struct MIOVF_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Overflow Flag
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Overflow Flag
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Overflow Flag
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Overflow Flag
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Overflow Flag
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Overflow Flag
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Overflow Flag
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Overflow Flag
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MIOVF_REG
{
    Uint32 all;
    struct MIOVF_BITS bit;
};

struct MIFRC_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Force
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Force
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Force
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Force
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Force
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Force
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Force
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Force
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MIFRC_REG
{
    Uint32 all;
    struct MIFRC_BITS bit;
};

struct MICLR_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Flag Clear
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Flag Clear
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Flag Clear
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Flag Clear
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Flag Clear
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Flag Clear
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Flag Clear
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Flag Clear
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MICLR_REG
{
    Uint32 all;
    struct MICLR_BITS bit;
};

struct MICLROVF_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Overflow Flag Clear
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Overflow Flag Clear
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Overflow Flag Clear
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Overflow Flag Clear
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Overflow Flag Clear
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Overflow Flag Clear
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Overflow Flag Clear
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Overflow Flag Clear
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MICLROVF_REG
{
    Uint32 all;
    struct MICLROVF_BITS bit;
};

struct MIER_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Interrupt Enable
    Uint32 INT2  : 1;  // 1 Task 2 Interrupt Enable
    Uint32 INT3  : 1;  // 2 Task 3 Interrupt Enable
    Uint32 INT4  : 1;  // 3 Task 4 Interrupt Enable
    Uint32 INT5  : 1;  // 4 Task 5 Interrupt Enable
    Uint32 INT6  : 1;  // 5 Task 6 Interrupt Enable
    Uint32 INT7  : 1;  // 6 Task 7 Interrupt Enable
    Uint32 INT8  : 1;  // 7 Task 8 Interrupt Enable
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MIER_REG
{
    Uint32 all;
    struct MIER_BITS bit;
};

struct MIRUN_BITS
{                      // bits description
    Uint32 INT1  : 1;  // 0 Task 1 Run Status
    Uint32 INT2  : 1;  // 1 Task 2 Run Status
    Uint32 INT3  : 1;  // 2 Task 3 Run Status
    Uint32 INT4  : 1;  // 3 Task 4 Run Status
    Uint32 INT5  : 1;  // 4 Task 5 Run Status
    Uint32 INT6  : 1;  // 5 Task 6 Run Status
    Uint32 INT7  : 1;  // 6 Task 7 Run Status
    Uint32 INT8  : 1;  // 7 Task 8 Run Status
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union MIRUN_REG
{
    Uint32 all;
    struct MIRUN_BITS bit;
};

struct SOFTINTEN_BITS
{                      // bits description
    Uint32 TASK1 : 1;  // 0 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK2 : 1;  // 1 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK3 : 1;  // 2 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK4 : 1;  // 3 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK5 : 1;  // 4 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK6 : 1;  // 5 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK7 : 1;  // 6 Configure Software Interrupt or End of Task interrupt.
    Uint32 TASK8 : 1;  // 7 Configure Software Interrupt or End of Task interrupt.
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union SOFTINTEN_REG
{
    Uint32 all;
    struct SOFTINTEN_BITS bit;
};

struct SOFTINTFRC_BITS
{                      // bits description
    Uint32 TASK1 : 1;  // 0 Force CLA software interrupt for the corresponding task.
    Uint32 TASK2 : 1;  // 1 Force CLA software interrupt for the corresponding task.
    Uint32 TASK3 : 1;  // 2 Force CLA software interrupt for the corresponding task.
    Uint32 TASK4 : 1;  // 3 Force CLA software interrupt for the corresponding task.
    Uint32 TASK5 : 1;  // 4 Force CLA software interrupt for the corresponding task.
    Uint32 TASK6 : 1;  // 5 Force CLA software interrupt for the corresponding task.
    Uint32 TASK7 : 1;  // 6 Force CLA software interrupt for the corresponding task.
    Uint32 TASK8 : 1;  // 7 Force CLA software interrupt for the corresponding task.
    Uint32 rsvd1 : 8;  // 15:8 Reserved
    Uint32 rsvd2 : 16; // 31:16 Reserved
};

union SOFTINTFRC_REG
{
    Uint32 all;
    struct SOFTINTFRC_BITS bit;
};

struct CLA_REGS
{
    Uint32 MVECT1;                   // Task Interrupt Vector
    Uint32 MVECT2;                   // Task Interrupt Vector
    Uint32 MVECT3;                   // Task Interrupt Vector
    Uint32 MVECT4;                   // Task Interrupt Vector
    Uint32 MVECT5;                   // Task Interrupt Vector
    Uint32 MVECT6;                   // Task Interrupt Vector
    Uint32 MVECT7;                   // Task Interrupt Vector
    Uint32 MVECT8;                   // Task Interrupt Vector
    union MCTL_REG MCTL;             // Control Register
    union MIFR_REG MIFR;             // Interrupt Flag Register
    union MIOVF_REG MIOVF;           // Interrupt Overflow Flag Register
    union MIFRC_REG MIFRC;           // Interrupt Force Register
    union MICLR_REG MICLR;           // Interrupt Flag Clear Register
    union MICLROVF_REG MICLROVF;     // Interrupt Overflow Flag Clear Register
    union MIER_REG MIER;             // Interrupt Enable Register
    union MIRUN_REG MIRUN;           // Interrupt Run Status Register
    Uint32 _MPC;                     // CLA Program Counter
    union SOFTINTEN_REG SOFTINTEN;   // CLA Software Interrupt Enable Register
    union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register
};

//---------------------------------------------------------------------------
// CLA External References & Function Declarations:
//

#ifdef __CORE0__
extern volatile struct CLA_REGS Cla1Regs;
#endif
#ifdef __cplusplus
}
#endif /* extern "C" */

#endif

//===========================================================================
// End of file.
//===========================================================================
